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OpenMP on the Low-Power TI Keystone II ARM/DSP System-on-Chip

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dc.contributor.authorStotzer, Eric
dc.contributor.authorJayaraj, Ajay
dc.contributor.authorAli, Murtaza
dc.contributor.authorFriedmann, Arnon
dc.contributor.authorMitra, Gaurav
dc.contributor.authorRendell, Alistair
dc.contributor.authorLintault, Ian
dc.date.accessioned2015-12-10T23:22:27Z
dc.date.issued2013
dc.date.updated2016-02-24T10:58:14Z
dc.description.abstractThe Texas Instrument (TI) Keystone II architecture integrates an octa-core C66X DSP with a quad-core ARM Cortex A15 MPCore processor in a non-cache coherent shared memory environment. This System-on-a-Chip (SoC) offers very high Floating Point Operations
dc.identifier.issn0302-9743
dc.identifier.urihttp://hdl.handle.net/1885/66522
dc.publisherSpringer
dc.rightshttp://www.sherpa.ac.uk/romeo/issn/0302-9743/..."Author's post-print on author's personal website, institutional repository, funder's designated repository" from SHERPA/RoMEO site (as at 26/08/16).
dc.sourceLecture Notes in Computer Science (LNCS)
dc.subjectKeywords: Current processors; Floating point operations per seconds; Multi-core dsp; Performance data; Shared memory; System on chips; System-on-a-chip; Texas Instruments; Application specific integrated circuits; Arches; ARM processors; Computer architecture; Elec
dc.titleOpenMP on the Low-Power TI Keystone II ARM/DSP System-on-Chip
dc.typeJournal article
dcterms.accessRightsOpen Access
local.bibliographicCitation.issueIWOMP 2013
local.bibliographicCitation.lastpage127
local.bibliographicCitation.startpage114
local.contributor.affiliationStotzer, Eric, Texas Instruments
local.contributor.affiliationJayaraj, Ajay, Texas Instruments
local.contributor.affiliationAli, Murtaza, Texas Instruments
local.contributor.affiliationFriedmann, Arnon, Texas Instruments
local.contributor.affiliationMitra, Gaurav, College of Engineering and Computer Science, ANU
local.contributor.affiliationRendell, Alistair, College of Engineering and Computer Science, ANU
local.contributor.affiliationLintault, Ian, NCore HPC
local.contributor.authoruidMitra, Gaurav, u4262869
local.contributor.authoruidRendell, Alistair, u9507815
local.description.embargo2037-12-31
local.description.notesImported from ARIES
local.identifier.absfor080304 - Concurrent Programming
local.identifier.absseo970108 - Expanding Knowledge in the Information and Computing Sciences
local.identifier.ariespublicationu4334215xPUB1298
local.identifier.citationvolume8122
local.identifier.doi10.1007/978-3-642-40698-0_9
local.identifier.scopusID2-s2.0-84883289743
local.type.statusPublished Version

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