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OpenMP on the Low-Power TI Keystone II ARM/DSP System-on-Chip

Date

Authors

Stotzer, Eric

Jayaraj, Ajay

Ali, Murtaza

Friedmann, Arnon

Mitra, Gaurav

Rendell, Alistair

Lintault, Ian

Publisher

Springer

Abstract

The Texas Instrument (TI) Keystone II architecture integrates an octa-core C66X DSP with a quad-core ARM Cortex A15 MPCore processor in a non-cache coherent shared memory environment. This System-on-a-Chip (SoC) offers very high Floating Point Operations

Keywords

Keywords: Current processors; Floating point operations per seconds; Multi-core dsp; Performance data; Shared memory; System on chips; System-on-a-chip; Texas Instruments; Application specific integrated circuits; Arches; ARM processors; Computer architecture; Elec

URI

http://hdl.handle.net/1885/66522

Collections

ANU Research Publications

Source

Lecture Notes in Computer Science (LNCS)

Type

Journal article

Access Statement

Open Access

DOI

10.1007/978-3-642-40698-0_9

Restricted until

2037-12-31

Downloads

File

Description

01_Stotzer_OpenMP_on_the_Low-Power_TI_2013.pdf (202.2 KB)