OpenMP on the Low-Power TI Keystone II ARM/DSP System-on-Chip
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Authors
Stotzer, Eric
Jayaraj, Ajay
Ali, Murtaza
Friedmann, Arnon
Mitra, Gaurav
Rendell, Alistair
Lintault, Ian
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Springer
Abstract
The Texas Instrument (TI) Keystone II architecture integrates an octa-core C66X DSP with a quad-core ARM Cortex A15 MPCore processor in a non-cache coherent shared memory environment. This System-on-a-Chip (SoC) offers very high Floating Point Operations
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Lecture Notes in Computer Science (LNCS)
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Open Access
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Restricted until
2037-12-31
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