Implementation and optimization of the OpenMP accelerator model for the TI Keystone II architecture
| dc.contributor.author | Mitra, Gaurav | |
| dc.contributor.author | Stotzer, Eric | |
| dc.contributor.author | Jayaraj, Ajay | |
| dc.contributor.author | Rendell, Alistair | |
| dc.coverage.spatial | Bahia, Brazil | |
| dc.date.accessioned | 2015-12-10T23:13:45Z | |
| dc.date.available | 2015-12-10T23:13:45Z | |
| dc.date.created | September 28-30 2014 | |
| dc.date.issued | 2014 | |
| dc.date.updated | 2015-12-10T09:41:42Z | |
| dc.description.abstract | The TI Keystone II architecture provides a unique combination of ARM Cortex-A15 processors with high performance TI C66x floating-point DSPs on a single low-power System-on-chip (SoC). Commercially available systems such as the HP Proliant m800 and nCore | |
| dc.identifier.isbn | 9783319114538 | |
| dc.identifier.uri | http://hdl.handle.net/1885/64566 | |
| dc.publisher | Springer | |
| dc.relation.ispartofseries | 10th International Workshop on OpenMP (IWOMP 2014) | |
| dc.source | LNCS 8766 - Using and Improving OpenMP for Devices, Tasks, and More | |
| dc.source.uri | http://download.springer.com/static/pdf/362/bok%253A978-3-319-11454-5.pdf?auth66=1424661287_822374933dbebbd4863ec0288eef2930&ext=.pdf | |
| dc.title | Implementation and optimization of the OpenMP accelerator model for the TI Keystone II architecture | |
| dc.type | Conference paper | |
| local.bibliographicCitation.lastpage | 214 | |
| local.bibliographicCitation.startpage | 202 | |
| local.contributor.affiliation | Mitra, Gaurav, College of Engineering and Computer Science, ANU | |
| local.contributor.affiliation | Stotzer, Eric, Texas Instruments | |
| local.contributor.affiliation | Jayaraj, Ajay, Texas Instruments | |
| local.contributor.affiliation | Rendell, Alistair, College of Engineering and Computer Science, ANU | |
| local.contributor.authoruid | Mitra, Gaurav, u4262869 | |
| local.contributor.authoruid | Rendell, Alistair, u9507815 | |
| local.description.notes | Imported from ARIES | |
| local.description.refereed | Yes | |
| local.identifier.absfor | 100605 - Performance Evaluation; Testing and Simulation of Reliability | |
| local.identifier.absfor | 080304 - Concurrent Programming | |
| local.identifier.absfor | 080302 - Computer System Architecture | |
| local.identifier.absseo | 970108 - Expanding Knowledge in the Information and Computing Sciences | |
| local.identifier.ariespublication | a383154xPUB962 | |
| local.identifier.doi | 10.1007/978-3-319-11454-5 | |
| local.identifier.scopusID | 2-s2.0-84921670367 | |
| local.type.status | Published Version |