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Implementation and optimization of the OpenMP accelerator model for the TI Keystone II architecture

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Date

2014

Authors

Mitra, Gaurav
Stotzer, Eric
Jayaraj, Ajay
Rendell, Alistair

Journal Title

Journal ISSN

Volume Title

Publisher

Springer

Abstract

The TI Keystone II architecture provides a unique combination of ARM Cortex-A15 processors with high performance TI C66x floating-point DSPs on a single low-power System-on-chip (SoC). Commercially available systems such as the HP Proliant m800 and nCore

Description

Keywords

Citation

URI

http://hdl.handle.net/1885/64566

Collections

ANU Research Publications

Source

LNCS 8766 - Using and Improving OpenMP for Devices, Tasks, and More

Type

Conference paper

Book Title

Entity type

Access Statement

License Rights

DOI

10.1007/978-3-319-11454-5

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