A Simple Performance Model for Multithreaded Applications Executing on Non-Uniform Memory Access Computers

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dc.contributor.authorYang, Rui
dc.contributor.authorAntony, Joseph
dc.contributor.authorRendell, Alistair
dc.coverage.spatialSeoul Korea
dc.date.accessioned2015-12-10T22:23:20Z
dc.date.createdJune 25-27 2009
dc.date.issued2009
dc.date.updated2016-02-24T10:17:33Z
dc.description.abstractIn this work, we extend and evaluate a simple performance model to account for NUMA and bandwidth effects for single and multi-threaded calculations within the Gaussian 03 computational chemistry code on a contemporary multi-core, NUMA platform. By using
dc.identifier.isbn9780769537382
dc.identifier.urihttp://hdl.handle.net/1885/52737
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE Inc)
dc.relation.ispartofseriesIEEE International Conference on High Performance Computing and Communications 2009
dc.sourceProceedings of the 11th IEEE International Conference on High Performance Computing and Communications (HPCC 2009)
dc.subjectKeywords: Bandwidth constraint; Computational chemistry; Extended model; Gaussians; Load-Balancing; Multi core; Multi-threaded application; Multithreaded; Non uniform memory access; On chip interconnect; Performance Model; Single-threaded; Solaris; Computer science
dc.titleA Simple Performance Model for Multithreaded Applications Executing on Non-Uniform Memory Access Computers
dc.typeConference paper
local.bibliographicCitation.lastpage86
local.bibliographicCitation.startpage79
local.contributor.affiliationYang, Rui, College of Engineering and Computer Science, ANU
local.contributor.affiliationAntony, Joseph, College of Engineering and Computer Science, ANU
local.contributor.affiliationRendell, Alistair, College of Engineering and Computer Science, ANU
local.contributor.authoremailu3804972@anu.edu.au
local.contributor.authoruidYang, Rui, u3804972
local.contributor.authoruidAntony, Joseph, u2576015
local.contributor.authoruidRendell, Alistair, u9507815
local.description.embargo2037-12-31
local.description.notesImported from ARIES
local.description.refereedYes
local.identifier.absfor100605 - Performance Evaluation; Testing and Simulation of Reliability
local.identifier.absfor100604 - Memory Structures
local.identifier.ariespublicationu3594520xPUB254
local.identifier.doi10.1109/HPCC.2009.39
local.identifier.scopusID2-s2.0-70449584580
local.identifier.uidSubmittedByu3594520
local.type.statusPublished Version

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