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Barriers reconsidered, friendlier still!

dc.contributor.authorYang, Xi
dc.contributor.authorBlackburn, Stephen
dc.contributor.authorFrampton, Daniel
dc.contributor.authorHosking, Anthony
dc.coverage.spatialBeijing China
dc.date.accessioned2015-12-10T23:31:42Z
dc.date.createdJune 15-16 2012
dc.date.issued2012
dc.date.updated2016-02-24T08:51:05Z
dc.description.abstractRead and write barriers mediate access to the heap allowing the collector to control and monitor mutator actions. For this reason, barriers are a powerful tool in the design of any heap management algorithm, but the prevailing wisdom is that they impose significant costs. However, changes in hardware and workloads make these costs a moving target. Here, we measure the cost of a range of useful barriers on a range of modern hardware and workloads. We confirm some old results and overturn others. We evaluate the microarchitectural sensitivity of barrier performance and the differences among benchmark suites. We also consider barriers in context, focusing on their behavior when used in combination, and investigate a known pathology and evaluate solutions. Our results show that read and write barriers have average overheads as low as 5.4% and 0.9% respectively. We find that barrier overheads are more exposed on the workload provided by the modern DaCapo benchmarks than on old SPECjvm98 benchmarks. Moreover, there are differences in barrier behavior between in-order and out-of-order machines, and their respective memory subsystems, which indicate different barrier choices for different platforms. These changing costs mean that algorithm designers need to reconsider their design choices and the nature of their resulting algorithms in order to exploit the opportunities presented by modern hardware.
dc.identifier.isbn9781450313506
dc.identifier.urihttp://hdl.handle.net/1885/68764
dc.publisherConference Organising Committee
dc.relation.ispartofseriesACM SIGPLAN International Symposium on Memory Management (ISMM 2012)
dc.sourceInternational Symposium on Memory Management, ISMM
dc.subjectKeywords: Barrier performance; Benchmark suites; Control and monitor; Garbage collection; Java; Memory management; Memory subsystems; Moving targets; Out of order; Write barriers; Algorithms; Design; Hardware; Java programming language; Costs Garbage collection; Java; Memory management; Write barriers
dc.titleBarriers reconsidered, friendlier still!
dc.typeConference paper
local.bibliographicCitation.lastpage47
local.bibliographicCitation.startpage37
local.contributor.affiliationYang, Xi, College of Engineering and Computer Science, ANU
local.contributor.affiliationBlackburn, Stephen, College of Engineering and Computer Science, ANU
local.contributor.affiliationFrampton, Daniel, College of Engineering and Computer Science, ANU
local.contributor.affiliationHosking, Anthony, Purdue University
local.contributor.authoruidYang, Xi, u4632562
local.contributor.authoruidBlackburn, Stephen, u3789498
local.contributor.authoruidFrampton, Daniel, u3293014
local.description.embargo2037-12-31
local.description.notesImported from ARIES
local.description.refereedYes
local.identifier.absfor080308 - Programming Languages
local.identifier.absfor100604 - Memory Structures
local.identifier.ariespublicationf5625xPUB1822
local.identifier.doi10.1145/2426642.2259004
local.identifier.scopusID2-s2.0-84872721355
local.identifier.thomsonID000313659800004
local.type.statusPublished Version

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