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Parallel binary reflected gray code sequence generation on multicore architectures

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dc.contributor.authorAli, Muhammad
dc.contributor.authorRumi, Shakila Khan
dc.date.accessioned2015-12-10T23:07:51Z
dc.date.issued2014
dc.date.updated2015-12-10T09:02:21Z
dc.description.abstractWe propose a novel parallel algorithm for generating all the sequences of binary reflected Gray code for a given number of bits as input, targeting machines with multicore architectures. A theoretical analysis of work and span, as well as parallelism of this algorithm, is carried out following a multithreaded implementation using Cilk++ on a multicore machine. Theoretical analysis of this algorithm shows a parallelism of Θ(2n/log n) and achieves a linear speedup on 12 cores for input data of sufficiently large size.
dc.identifier.issn1744-5760
dc.identifier.urihttp://hdl.handle.net/1885/63036
dc.publisherCarfax Publishing, Taylor & Francis Group
dc.sourceInternational Journal of Parallel, Emergent and Distributed Systems
dc.titleParallel binary reflected gray code sequence generation on multicore architectures
dc.typeJournal article
local.bibliographicCitation.issue5
local.bibliographicCitation.lastpage520
local.bibliographicCitation.startpage513
local.contributor.affiliationAli, Muhammad, College of Engineering and Computer Science, ANU
local.contributor.affiliationRumi, Shakila Khan, Khulna University of Engineering & Technology
local.contributor.authoruidAli, Muhammad, u4616239
local.description.embargo2037-12-31
local.description.notesImported from ARIES
local.identifier.absfor080201 - Analysis of Algorithms and Complexity
local.identifier.absseo970108 - Expanding Knowledge in the Information and Computing Sciences
local.identifier.ariespublicationa383154xPUB763
local.identifier.citationvolume29
local.identifier.doi10.1080/17445760.2013.822498
local.identifier.scopusID2-s2.0-84901807815
local.type.statusPublished Version

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