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DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time

Date

Authors

Shi, W.

Wang, Z.

Ren, H.

Cao, Ting

Chen, W.

Su, B.

Lu, H.

Publisher

IEEE

Abstract

Embedded application environments require both high performance and low power. Architectures exploiting instruction-level parallelism (ILP) at compile time, such as very long instruction word (VLIW) and transport triggered architecture (TTA), may satisfy

Keywords

Keywords: Asynchronous circuits; Asynchronous processors; Compile time; Data source; Embedded application; Instruction-level parallelism; Low Power; Micro architectures; Pipelined processor; Power Consumption; Power dissipation; Transport triggered architecture; Ve

URI

http://hdl.handle.net/1885/83666

Collections

ANU Research Publications

Source

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Type

Conference paper

DOI

10.1109/ICCD.2010.5647721

Restricted until

2037-12-31

Downloads

File

Description

01_Shi_DSS:_Applying_asynchronous_2010.pdf (2.05 MB)

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