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CycleCounter: an Efficient and Accurate UltraSPARC III CPU Simulation Module

Strazdins, Peter


This paper presents a novel technique for cycle-accurate simulation of the Central Processing Unit (CPU) of a modern superscalar processor, the UltraSPARC III Cu processor. The technique is based on adding a module to an existing fetch-decode-execute style of CPU simulator, rather than the traditional method of fully implementing the CPU pipeline and microarchitecture. The main functions of the module are the simulation of instruction grouping, register interlocks and the store buffer,...[Show more]

CollectionsANU Research Publications
Date published: 2005
Type: Working/Technical Paper


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