Electrical characterization impurity-disordering induced defects in n-GaAs using native oxide layers
Date
2002
Authors
Deenapanray, P.N.K
Jagadish, Chennupati
Tan, Hark Hoe
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Publisher
Springer-Verlag
Abstract
Defects created in rapid thermally annealed n-GaAs epilayers capped with native oxide layers have been investigated using deep-level transient spectroscopy (DLTS). The native oxide layers were formed at room temperature using pulsed anodic oxidation. A hole trap H0, due to either interface states or injection of interstitials, is observed around the detection limit of DLTS in oxidized samples. Rapid thermal annealing introduces three additional minority-carrier traps H1 (EV+0.44 eV), H2 (EV+0.73 eV), and H3 (EV+0.76 eV). These hole traps are introduced in conjunction with electron traps S1 (EC.0.23 eV) and S2 (EC.0.45 eV), which are observed in the same epilayers following disordering using SiO2 capping layers. We also provide evidence that a hole trap whose DLTS peak overlaps with that of EL2 is present in the disordered n-GaAs layers. The mechanisms through which these hole traps are created are discussed. Capacitance–voltage measurements reveal that impurity-free disordering using native oxides of GaAs produced higher free-carrier compensation compared to SiO2 capping layers.
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Keywords
defects, n-GaAs, native oxide layers, DLTS, deep-level transient spectroscopy, anodic oxidation, traps, epilayers, capacitance-voltage measurements
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Journal article