Hardware-Software Integrated Acceleration for Scientific Computing Applications

Abstract

With the advancement of semiconductor manufacturing processes and the bottleneck of chip power consumption, the focus of chip performance improvement has shifted from enhancing its electrical characteristics to utilizing parallel architectures and proprietary circuits. Unfortunately, software has not kept pace with hardware advancements, making it difficult to fully leverage the performance capabilities of the hardware. However, acceleration software requires meticulous design and incremental program development, which makes it extremely complex. This complexity impacts the performance of the software, affecting both research and production. This thesis aims to establish a connection between software performance requirements and the selection of specific acceleration mechanisms, proposing a policy for hardware-software integrated acceleration on single-machine system.

This thesis is structured into two parts. In the first part of the thesis, it summarizes and organizes the requirements during the scientific computing software acceleration process, as well as the operational characteristics of software and hardware, into Performance, Cost, and Power Consumption (PC2) principles to guide software acceleration. Various requirements of acceleration may be categorizes by performance, cost, and power consumption. This thesis discusses the correlation between these three aspects and the characteristics of software and hardware, indicates the conflicts among these three aspects, and summarize a strategy to balance these three aspects in order to make choice of software acceleration mechanisms.

In the second part of this thesis, it validates the PC2 principles through acceleration examples of four specific scientific computing scenarios. The specific acceleration mechanisms discovered and the software and hardware architectures designed in these four scenarios constitute the main contribution of this thesis. The first scenario demonstrates the acceleration of a pathway network software used in early drug discovery on a multi-core processor platform using an embarrassing parallel algorithm. The second scenario illustrates the acceleration of a toolkit for polyploid genome scaffolding on a multi-core processor platform by re-modeling and segmenting the original runtime process and applying partial real-time embedded system resource management techniques. The third scenario showcases the enhancement of 3D optical flow evaluation in terms of effectiveness and performance on a GPGPU platform by replacing pure geometric algorithms with fully vectorized deep convolutional neural networks and quantizing the network to half-precision. The fourth scenario demonstrates the real-time update and high-frequency tracking of target areas using a single RGB camera with extremely low power consumption, achieved through the design and fabrication of custom ASIC hardware. These scenarios have achieved state-of-the-art performance or energy efficiency in their respective fields. Show more