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Systolic architectures for parallel implementation of digital filters

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dc.contributor.authorZhou, Bing Bing
dc.date.accessioned2017-12-20T23:46:10Z
dc.date.available2017-12-20T23:46:10Z
dc.date.copyright1988
dc.date.issued1988
dc.date.updated2017-11-22T23:06:51Z
dc.format.extentx, 123 leaves
dc.identifier.otherb1695963
dc.identifier.urihttp://hdl.handle.net/1885/138419
dc.language.isoenen_AU
dc.subject.lcshSignal processing Digital techniques
dc.subject.lcshSystolic array circuits
dc.subject.lcshComputer architecture
dc.titleSystolic architectures for parallel implementation of digital filtersen_AU
dc.typeThesis (PhD)en_AU
dcterms.valid1988en_AU
local.contributor.affiliationThe Australian National Universityen_AU
local.description.notesThesis (Ph.D.)--Australian National University, 1988. This thesis has been made available through exception 200AB to the Copyright Act.en_AU
local.identifier.doi10.25911/5d6f9be3e31b4
local.identifier.proquestYes
local.mintdoimint
local.type.degreeDoctor of Philosophy (PhD)en_AU

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