Scalable Quantum Computing with Two-Dimensional Arrays of Trapped Ions Enabled by Fast Gates

Abstract

Realising large-scale quantum computation in the near future will require increasing the number of low-error two-qubit gates that can be implemented on a quantum computer before decoherence. One of the biggest challenges facing current trapped ion quantum computers is implementing high-speed two-qubit operations, whilst increasing the number of qubits. One of the most promising proposals for overcoming current limitations is the use of ultra-fast pulses to implement fast two-qubit gates between nearest-neighbour pairs of ions. In this thesis, I investigate these ‘fast gates’ in two-dimensional arrays of microtraps, each containing a single ion. I argue that two-dimensional architectures allow for a significant reduction in the number of two-qubit gates required for a particular computation, as compared to one-dimensional ion chains. I demonstrate this reduction for a quantum simulation of a 40-mode Fermi-Hubbard Hamiltonian. I develop an efficient scheme that allows fast gates to be numerically optimised for two-dimensional geometries. I find that this optimisation scheme is capable of designing gates that are faster, higher fidelity, and require lower laser repetition rates. Using this scheme, I find that high-speed two-qubit gates can be optimised for two-dimensional architectures, with fidelities well above thresholds required for fault tolerant error correction, around 99.99%. Furthermore, I find that fast gates in these architectures are robust to the presence of large numbers of surrounding ions. Following previous studies [1, 2] which have identified pulse imperfections as a dominant source of error in fast gates, I perform a worst-case error analysis. I find the fast gates presented in this thesis to require very small errors in single-qubit rotations, and I present recommendations for achieving those requirements. I also investigate other experimental considerations, and make recommendations for overcoming other technical challenges in realising fast gates.