Implementation and optimization of the OpenMP accelerator model for the TI Keystone II architecture
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Mitra, Gaurav; Stotzer, Eric; Jayaraj, Ajay; Rendell, Alistair
Description
The TI Keystone II architecture provides a unique combination of ARM Cortex-A15 processors with high performance TI C66x floating-point DSPs on a single low-power System-on-chip (SoC). Commercially available systems such as the HP Proliant m800 and nCore
Collections | ANU Research Publications |
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Date published: | 2014 |
Type: | Conference paper |
URI: | http://hdl.handle.net/1885/64566 |
Source: | LNCS 8766 - Using and Improving OpenMP for Devices, Tasks, and More |
DOI: | 10.1007/978-3-319-11454-5 |
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