Stotzer, EricJayaraj, AjayAli, MurtazaFriedmann, ArnonMitra, GauravRendell, AlistairLintault, Ian2015-12-100302-9743http://hdl.handle.net/1885/66522The Texas Instrument (TI) Keystone II architecture integrates an octa-core C66X DSP with a quad-core ARM Cortex A15 MPCore processor in a non-cache coherent shared memory environment. This System-on-a-Chip (SoC) offers very high Floating Point Operationshttp://www.sherpa.ac.uk/romeo/issn/0302-9743/..."Author's post-print on author's personal website, institutional repository, funder's designated repository" from SHERPA/RoMEO site (as at 26/08/16).Keywords: Current processors; Floating point operations per seconds; Multi-core dsp; Performance data; Shared memory; System on chips; System-on-a-chip; Texas Instruments; Application specific integrated circuits; Arches; ARM processors; Computer architecture; Elec201310.1007/978-3-642-40698-0_92016-02-24