Systolic architectures for parallel implementation of digital filters

Zhou, Bing Bing2017-12-202017-12-201988b1695963http://hdl.handle.net/1885/138419x, 123 leavesenSignal processing Digital techniquesSystolic array circuitsComputer architectureSystolic architectures for parallel implementation of digital filters198810.25911/5d6f9be3e31b42017-11-22