Vernet, M.Jeantet, O.Parashar, A.Degoirat, H.Verma, P.K.Yadav, S.K.Chawla, K.Atif, MuhammadHanda, T.Sharad, S.Penaka, G P2015-12-13May 22-259781457702259http://hdl.handle.net/1885/72127This paper presents an embedded DRAM memory design on 32nm Low Power process using recently introduced Capacitor Over Low-K (COLK) bitcell architecture [1]. It consists in the 1st functional silicon demonstration of 32nm embedded DRAM macrocell with unrivalled density of 0.1mm2/Mbit. The memory features a high performance sense amplifier with tunable reference level, an overdriven reliability-friendly row decoder with adjusted voltage and a low swing although flexible data transfer scheme. Making low cost eDRAM with 2.5ns cycle time available on 32nm low power platform opens new opportunities for consumer electronics devices such as advanced smartphones or graphical handheld devices.Keywords: 32nm; COLK capacitor; eDRAM; Embedded dynamic random access memory; Low costs; Low Power; Sense amplifier; Capacitors; Consumer electronics; Data transfer; Memory architecture; Dynamic random access storage 32nm; COLK capacitor; eDRAM; embedded dynamic random access memory; low cost; low power; reliability; sense amplifier201110.1109/IMW.2011.58732022016-02-24