DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time

Shi, W.Wang, Z.Ren, H.Cao, TingChen, W.Su, B.Lu, H.2015-12-13October 3-9781424489350http://hdl.handle.net/1885/83666Embedded application environments require both high performance and low power. Architectures exploiting instruction-level parallelism (ILP) at compile time, such as very long instruction word (VLIW) and transport triggered architecture (TTA), may satisfyKeywords: Asynchronous circuits; Asynchronous processors; Compile time; Data source; Embedded application; Instruction-level parallelism; Low Power; Micro architectures; Pipelined processor; Power Consumption; Power dissipation; Transport triggered architecture; VeDSS: Applying asynchronous techniques to architectures exploiting ILP at compile time201010.1109/ICCD.2010.56477212016-02-24