Efficient I/O Virtualisation in Asymmetric Multiprocessor Architectures

Abstract

Server virtualisation is increasingly popular but still suffers from poor I/O performance. There are several methods to address the problem. One solution is the side-core approach to offload virtualisation I/O processing on a dedicated core, which offers close to bare-metal performance without sacrificing important virtualisation features. Although the number of cores is continually increasing and the financial cost per core is dropping, considering the characteristics of I/O processing, the side-core approach can be more efficient with an asymmetric multi-processor (AMP) rather than a symmetric multi-processor. The broad objective of this work is to determine exactly how to design a dedicated core to offload I/O processing, typically a small core of an AMP, that can save power, energy, and area while retaining the performance of virtualised scientific workloads at a tolerable cost. Various strategies are employed to achieve this goal, including an analysis of intrinsic characteristics of I/O processing, experimental studies with AMP emulations, and architectural simulations to refine the preliminary results. Our methodology is first to use real processors to determine appropriate design parameters. We perform extensive experiments to evaluate the potential gain from using a side-core as well as investigate the overheads of VM I/O processing on virtualised systems with/without off-loading. This reveals the significant impact of off-loading on improving performance as well as reducing architectural overheads, such as cache and translation look-ahead buffer (TLB) misses. Then, we determine a suitable side-core design by using real processors to emulate an AMP. Our results show that a narrow, fast (high clock) in-order pipeline, with small first/second level caches without hardware data pre-fetch and a simple branch prediction unit are the desired features for an efficient side-core. We use not only scientific but also commercial workloads and both demonstrate similar results. However, these conclusions are limited by physically available configurations.Second, we use simulations to explore the parameter space in greater detail and perform an energy-delay-area analysis. We focus on TLBs and caches, which appear to have a remarkable impact on performance. We extend core/memory models of an architectural simulator and perform full-machine simulations of an AMP with VM I/O offload on the small core. The structural parameters of the L1/L2 caches and TLBs are scaled while taking into account their size, associativity, access latency and performance (hit ratio). These architectural simulation results are combined with power and energy simulations. The resulting energy-delay analysis shows that the optimal features of an efficient side-core are smaller and simpler L1/L2 caches, and larger L1/L2 TLBs, compared with an Intel Atom processor. It also reveals that a processor module consisting of two big cores and a small side-core of our design can reduce average power, energy, and area by 9.2%, 8%, and 24.4%, respectively, compared with a module of three big cores (the AMD K10), while retaining performance. Show more