DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time

Shi, W.; Wang, Z.; Ren, H.; Cao, Ting; Chen, W.; Su, B.; Lu, H.

doi:10.1109/ICCD.2010.5647721

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DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time

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Shi, W.; Wang, Z.; Ren, H.; Cao, Ting; Chen, W.; Su, B.; Lu, H.

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Embedded application environments require both high performance and low power. Architectures exploiting instruction-level parallelism (ILP) at compile time, such as very long instruction word (VLIW) and transport triggered architecture (TTA), may satisfy

Collections	ANU Research Publications
Date published:	2010
Type:	Conference paper
URI:	http://hdl.handle.net/1885/83666
Source:	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
DOI:	10.1109/ICCD.2010.5647721

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DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time

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