DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time
Embedded application environments require both high performance and low power. Architectures exploiting instruction-level parallelism (ILP) at compile time, such as very long instruction word (VLIW) and transport triggered architecture (TTA), may satisfy
|Collections||ANU Research Publications|
|Source:||Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors|
|01_Shi_DSS:_Applying_asynchronous_2010.pdf||2.09 MB||Adobe PDF||Request a copy|
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