Vernet, M.; Jeantet, O.; Parashar, A.; Degoirat, H.; Verma, P.K.; Yadav, S.K.; Chawla, K.; Atif, Muhammad; Handa, T.; Sharad, S.; Penaka, G P
This paper presents an embedded DRAM memory design on 32nm Low Power process using recently introduced Capacitor Over Low-K (COLK) bitcell architecture . It consists in the 1st functional silicon demonstration of 32nm embedded DRAM macrocell with unrivalled density of 0.1mm2/Mbit. The memory features a high performance sense amplifier with tunable reference level, an overdriven reliability-friendly row decoder with adjusted voltage and a low swing although flexible data transfer scheme....[Show more]
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