32nm embedded DRAM reaching 400MHz and 0.1mm/Mb on a low cost and low power process
This paper presents an embedded DRAM memory design on 32nm Low Power process using recently introduced Capacitor Over Low-K (COLK) bitcell architecture . It consists in the 1st functional silicon demonstration of 32nm embedded DRAM macrocell with unrivalled density of 0.1mm2/Mbit. The memory features a high performance sense amplifier with tunable reference level, an overdriven reliability-friendly row decoder with adjusted voltage and a low swing although flexible data transfer scheme....[Show more]
|Collections||ANU Research Publications|
|Source:||3rd IEEE International Memory Workshop, IMW 2011|
|01_Vernet_32nm_embedded_DRAM_reaching_2011.pdf||629 kB||Adobe PDF||Request a copy|
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