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32nm embedded DRAM reaching 400MHz and 0.1mm/Mb on a low cost and low power process

Vernet, M.; Jeantet, O.; Parashar, A.; Degoirat, H.; Verma, P.K.; Yadav, S.K.; Chawla, K.; Atif, Muhammad; Handa, T.; Sharad, S.; Penaka, G P

Description

This paper presents an embedded DRAM memory design on 32nm Low Power process using recently introduced Capacitor Over Low-K (COLK) bitcell architecture [1]. It consists in the 1st functional silicon demonstration of 32nm embedded DRAM macrocell with unrivalled density of 0.1mm2/Mbit. The memory features a high performance sense amplifier with tunable reference level, an overdriven reliability-friendly row decoder with adjusted voltage and a low swing although flexible data transfer scheme....[Show more]

CollectionsANU Research Publications
Date published: 2011
Type: Conference paper
URI: http://hdl.handle.net/1885/72127
Source: 3rd IEEE International Memory Workshop, IMW 2011
DOI: 10.1109/IMW.2011.5873202

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