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Defect engineering in annealed n-type GaAs epilayers using SiO 2 /Si 3 N 4 stacking layers

Deenapanray, Prakash; Martin, Anthony H; Jagadish, Chennupati

dc.contributor.authorDeenapanray, Prakash
dc.contributor.authorMartin, Anthony H
dc.contributor.authorJagadish, Chennupati
dc.date.accessioned2015-12-10T23:30:50Z
dc.date.available2015-12-10T23:30:50Z
dc.identifier.issn0003-6951
dc.identifier.urihttp://hdl.handle.net/1885/68349
dc.publisherAmerican Institute of Physics (AIP)
dc.sourceApplied Physics Letters
dc.titleDefect engineering in annealed n-type GaAs epilayers using SiO 2 /Si 3 N 4 stacking layers
dc.typeJournal article
local.description.notesImported from ARIES
local.description.refereedYes
local.identifier.citationvolume79
dc.date.issued2001
local.identifier.absfor020204 - Plasma Physics; Fusion Plasmas; Electrical Discharges
local.identifier.ariespublicationMigratedxPub1688
local.type.statusPublished Version
local.contributor.affiliationDeenapanray, Prakash, College of Physical and Mathematical Sciences, ANU
local.contributor.affiliationMartin, Anthony H, no formal affiliation
local.contributor.affiliationJagadish, Chennupati, College of Physical and Mathematical Sciences, ANU
local.bibliographicCitation.issue16
local.bibliographicCitation.startpage2561
local.bibliographicCitation.lastpage2563
dc.date.updated2015-12-10T11:09:43Z
CollectionsANU Research Publications

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