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Single core hardware module to implement partial encryption of compressed image

Reaz, Mamun Bin Ibne; Amin, Md. Syedul; Hashim, Fazida Hanim; Asaduzzaman, Khandaker

Description

Problem statement: Real-time secure image and video communication is challenging due to the processing time and computational requirement for encryption and decryption. In order to cope with these concerns, innovative image compression and encryption techniques are required. Approach: In this research, we have introduced partial encryption technique on compressed images and implemented the algorithm on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The compression...[Show more]

dc.contributor.authorReaz, Mamun Bin Ibne
dc.contributor.authorAmin, Md. Syedul
dc.contributor.authorHashim, Fazida Hanim
dc.contributor.authorAsaduzzaman, Khandaker
dc.date.accessioned2015-12-10T22:30:17Z
dc.identifier.issn1546-9239
dc.identifier.urihttp://hdl.handle.net/1885/55030
dc.description.abstractProblem statement: Real-time secure image and video communication is challenging due to the processing time and computational requirement for encryption and decryption. In order to cope with these concerns, innovative image compression and encryption techniques are required. Approach: In this research, we have introduced partial encryption technique on compressed images and implemented the algorithm on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The compression algorithm decomposes images into several different parts. We have used a secured encryption algorithm to encrypt only the crucial parts, which are considerably smaller than the original image, which result in significant reduction in processing time and computational requirement for encryption and decryption. The breadth-first traversal linear lossless quadtree decomposition method is used for the partial compression and RSA is used for the encryption. Results: Functional simulations were commenced to verify the functionality of the individual modules and the system on four different images. We have validated the advantage of the proposed approach through comparison, verification and analysis. The design has utilized 2928 units of LC with a system frequency of 13.42MHz. Conclusion: In this research, the FPGA prototyping of a partial encryption of compressed images using lossless quadtree compression and RSA encryption has been successfully implemented with minimum logic cells. It is found that the compression process is faster than the decompression process in linear quadtree approach. Moreover, the RSA simulations show that the encryption process is faster than the decryption process for all four images tested.
dc.publisherAsian Network for Scientific Information
dc.sourceAmerican Journal of Applied Sciences
dc.subjectKeywords: Data Encryption Standard (DES); Encryption algorithm; Encryption techniques; Field- Programmable Gate Arrays (FPGA); Partial encryption; Quadtree compression; Real-time secure image; Video communication
dc.titleSingle core hardware module to implement partial encryption of compressed image
dc.typeJournal article
local.description.notesImported from ARIES
local.identifier.citationvolume8
dc.date.issued2011
local.identifier.absfor080199 - Artificial Intelligence and Image Processing not elsewhere classified
local.identifier.ariespublicationf5625xPUB317
local.type.statusPublished Version
local.contributor.affiliationReaz, Mamun Bin Ibne, University Kebangsaan Malaysia
local.contributor.affiliationAmin, Md. Syedul, University Kebangsaan Malaysia
local.contributor.affiliationHashim, Fazida Hanim, University Kebangsaan Malaysia
local.contributor.affiliationAsaduzzaman, Khandaker, College of Physical and Mathematical Sciences, ANU
local.description.embargo2037-12-31
local.bibliographicCitation.issue6
local.bibliographicCitation.startpage566
local.bibliographicCitation.lastpage573
dc.date.updated2016-02-24T09:06:26Z
local.identifier.scopusID2-s2.0-79959419892
CollectionsANU Research Publications

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