Efficient Cycle-Accurate Simulation of the UltraSPARC III CPU
This paper presents a novel technique for cycleaccurate simulation of the Central Processing Unit (CPU) of a modern superscalar processor, the Ultra-SPARC III Cu processor. The technique is based on adding a module to an existing fetch-decode-execute style of CPU simulator, rather than the traditional method of fully modelling the CPU microarchitecture. It is also suitable for accurate SMP modelling. The main functions of the module are the simulation of instruction grouping, register...[Show more]
|Collections||ANU Research Publications|
|Source:||Conferences in Research and Practice in Information Technology (CRPIT), Volume 62|
|01_Strazdins_Efficient_Cycle-Accurate_2007.pdf||132.83 kB||Adobe PDF||Request a copy|
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