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Runtime Verification for LTL and TLTL

Bauer, Andreas; Leucker, Martin; Schallhart, Christian

Description

This article studies runtime verification of properties expressed either in lineartime temporal logic (LTL) or timed lineartime temporal logic (TLTL). It classifies runtime verification in identifying its distinguishing features to model checking and testing, respectively. It introduces a three-valued semantics (with truth values true, false, inconclusive) as an adequate interpretation as to whether a partial observation of a running system meets an LTL or TLTL property. For LTL, a conceptually...[Show more]

dc.contributor.authorBauer, Andreas
dc.contributor.authorLeucker, Martin
dc.contributor.authorSchallhart, Christian
dc.date.accessioned2015-12-08T22:42:15Z
dc.identifier.issn1049-331X
dc.identifier.urihttp://hdl.handle.net/1885/37011
dc.description.abstractThis article studies runtime verification of properties expressed either in lineartime temporal logic (LTL) or timed lineartime temporal logic (TLTL). It classifies runtime verification in identifying its distinguishing features to model checking and testing, respectively. It introduces a three-valued semantics (with truth values true, false, inconclusive) as an adequate interpretation as to whether a partial observation of a running system meets an LTL or TLTL property. For LTL, a conceptually simple monitor generation procedure is given, which is optimal in two respects: First, the size of the generated deterministic monitor is minimal, and, second, the monitor identifies a continuously monitored trace as either satisfying or falsifying a property as early as possible. The feasibility of the developed methodology is demontrated using a collection of real-world temporal logic specifications. Moreover, the presented approach is related to the properties monitorable in general and is compared to existing concepts in the literature. It is shown that the set of monitorable properties does not only encompass the safety and cosafety properties but is strictly larger. For TLTL, the same road map is followed by first defining a three-valued semantics. The corresponding construction of a timed monitor is more involved, yet, as shown, possible.
dc.publisherASME Digital Library
dc.sourceACM Transactions on Software Engineering and Methodology
dc.subjectKeywords: Assertion checkers; Linear time temporal logic; Partial observation; Road-maps; Running systems; Runtime verification; Temporal logic specifications; Three-valued; Truth values; Display devices; Model checking; Semantics; Temporal logic Assertion checkers; Monitors; Runtime verification
dc.titleRuntime Verification for LTL and TLTL
dc.typeJournal article
local.description.notesImported from ARIES
local.identifier.citationvolume20
dc.date.issued2011
local.identifier.absfor080309 - Software Engineering
local.identifier.ariespublicationu4963866xPUB143
local.type.statusPublished Version
local.contributor.affiliationBauer, Andreas, College of Engineering and Computer Science, ANU
local.contributor.affiliationLeucker, Martin, Technische Universitat Munchen
local.contributor.affiliationSchallhart, Christian, Technische Universitat Darmstadt
local.description.embargo2037-12-31
local.bibliographicCitation.issue4
local.bibliographicCitation.startpage69
local.identifier.doi10.1145/2000799.2000800
local.identifier.absseo890299 - Computer Software and Services not elsewhere classified
dc.date.updated2016-02-24T11:30:00Z
local.identifier.scopusID2-s2.0-79960344619
CollectionsANU Research Publications

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