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Portable performance on asymmetric multicore processors

Jibaja, Ivan; Cao, Ting; Blackburn, Stephen; McKinley, Kathryn

Description

Static and dynamic power constraints are steering chip manufacturers to build single-ISA Asymmetric Multicore Processors (AMPs) with big and small cores. To deliver on their energy efficiency potential, schedulers must consider core sensitivity, load balance, and the critical path. Applying these criteria effectively is challenging especially for complex and non-scalable multithreaded applications. We demonstrate that runtimes for managed languages, which are now ubiquitous, provide a unique...[Show more]

dc.contributor.authorJibaja, Ivan
dc.contributor.authorCao, Ting
dc.contributor.authorBlackburn, Stephen
dc.contributor.authorMcKinley, Kathryn
dc.date.accessioned2017-01-24T03:25:15Z
dc.date.available2017-01-24T03:25:15Z
dc.identifier.isbn9781450337786
dc.identifier.urihttp://hdl.handle.net/1885/112023
dc.description.abstractStatic and dynamic power constraints are steering chip manufacturers to build single-ISA Asymmetric Multicore Processors (AMPs) with big and small cores. To deliver on their energy efficiency potential, schedulers must consider core sensitivity, load balance, and the critical path. Applying these criteria effectively is challenging especially for complex and non-scalable multithreaded applications. We demonstrate that runtimes for managed languages, which are now ubiquitous, provide a unique opportunity to abstract over AMP complexity and inform scheduling with rich semantics such as thread priorities, locks, and parallelism— information not directly available to the hardware, OS, or application. We present the WASH AMP scheduler, which (1) automatically identifies and accelerates critical threads in concurrent, but non-scalable applications; (2) respects thread priorities; (3) considers core availability and thread sensitivity; and (4) proportionally schedules threads on big and small cores to optimize performance and energy. We introduce new dynamic analyses that identify critical threads and classify applications as sequential, scalable, or non-scalable. Compared to prior work, WASH improves performance by 20% and energy by 9% or more on frequency-scaled AMP hardware (not simulation). Performance advantages grow to 27% when asymmetry increases. Performance advantages are robust to a complex multithreaded adversary independently scheduled by the OS. WASH effectively identifies and optimizes a wider class of workloads than prior work.
dc.description.sponsorshipThis research is funded by the China Postdoctoral Science Foundation (No. 2015T80139), the National Natural Science Foundation of China (No. 61432018, 61272136, 61133005, 61221062), the National High Technology Research and Development Program of China (No. 2015AA01A303, 2015AA 011505), and the National Science Foundation of the United States (SHF-0910818).
dc.format.mimetypeapplication/pdf
dc.publisherAssociation for Computing Machinery
dc.relation.ispartofCGO '16 Proceedings of the 2016 International Symposium on Code Generation and Optimization, Barcelona, Spain - March 12 - 18, 2016
dc.rights© 2016 ACM
dc.titlePortable performance on asymmetric multicore processors
dc.typeConference paper
dc.date.issued2016
local.type.statusPublished Version
local.contributor.affiliationCao, T., The Australian National University
local.contributor.affiliationBlackburn, S. M., The Australian National University
local.bibliographicCitation.startpage24
local.bibliographicCitation.lastpage35
local.identifier.doi10.1145/2854038.2854047
dcterms.accessRightsOpen Access
CollectionsANU Research Publications

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