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How Small Can it Be?: The Design of a Cost-Effective Side-core for I/O Virtualization

Lee, Chung (Brian); Strazdins, Peter

Description

I/O processing in virtualization is expensive. It significantly slows down application performance running on virtual machines due to frequent context switches and resource contentions. There are several methods to address the problem. One solution is the side-core approach to carry out virtualization I/O processing on a dedicated core, which offers close to bare-metal performance, without sacrificing important virtualization features. Although the number of cores is continually increasing and...[Show more]

dc.contributor.authorLee, Chung (Brian)
dc.contributor.authorStrazdins, Peter
dc.coverage.spatialAmsterdam, The Netherlands
dc.date.accessioned2016-06-14T23:21:17Z
dc.date.created20-24 July 2015
dc.identifier.isbn9781467378123
dc.identifier.urihttp://hdl.handle.net/1885/103818
dc.description.abstractI/O processing in virtualization is expensive. It significantly slows down application performance running on virtual machines due to frequent context switches and resource contentions. There are several methods to address the problem. One solution is the side-core approach to carry out virtualization I/O processing on a dedicated core, which offers close to bare-metal performance, without sacrificing important virtualization features. Although the number of cores is continually increasing and the financial cost per core is dropping, considering the characteristics of I/O processing, the side-core approach can be more efficient with an asymmetric multi-processor (AMP) rather than a symmetric multi-processor (SMP). However, no thorough study has been performed to identify the requirements for the AMP to off-load the virtualization I/O tasks. In this paper, we examine various processor features, study behaviour of three different processors, and identify the most cost-efficient parameters for a side-core, both in terms of the financial cost and the number transistors. From our experimental analysis, we conclude that a narrow, fast (high clock) in-order pipeline, with small first/second level caches without hardware data prefetch, and a simple branch prediction unit are the desired features in a dedicated side-core for I/O processing. We estimate that this small side-core should consist of one fourth the transistor budget and perform I/O processing with only a 10% performance loss at the same frequency, compared to a big side-core
dc.publisherIEEE
dc.relation.ispartofseries2015 International Conference on High Performance Computing & Simulation (HPCS)
dc.sourceA Fault-Tolerant Gyrokinetic Plasma Application using the Sparse Grid Combination Technique
dc.titleHow Small Can it Be?: The Design of a Cost-Effective Side-core for I/O Virtualization
dc.typeConference paper
local.description.notesImported from ARIES
local.description.refereedYes
dc.date.issued2015
local.identifier.absfor080303 - Computer System Security
local.identifier.ariespublicationu4334215xPUB1572
local.type.statusPublished Version
local.contributor.affiliationLee, Chung (Brian), College of Engineering and Computer Science, ANU
local.contributor.affiliationStrazdins, Peter, College of Engineering and Computer Science, ANU
local.description.embargo2037-12-31
local.bibliographicCitation.startpage455
local.bibliographicCitation.lastpage462
local.identifier.doi10.1109/HPCC-CSS-ICESS.2015.302
local.identifier.absseo970108 - Expanding Knowledge in the Information and Computing Sciences
dc.date.updated2016-06-14T09:03:56Z
local.identifier.scopusID2-s2.0-84961737537
CollectionsANU Research Publications

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