How Small Can it Be?: The Design of a Cost-Effective Side-core for I/O Virtualization

Abstract

I/O processing in virtualization is expensive. It significantly slows down application performance running on virtual machines due to frequent context switches and resource contentions. There are several methods to address the problem. One solution is the side-core approach to carry out virtualization I/O processing on a dedicated core, which offers close to bare-metal performance, without sacrificing important virtualization features. Although the number of cores is continually increasing and the financial cost per core is dropping, considering the characteristics of I/O processing, the side-core approach can be more efficient with an asymmetric multi-processor (AMP) rather than a symmetric multi-processor (SMP). However, no thorough study has been performed to identify the requirements for the AMP to off-load the virtualization I/O tasks. In this paper, we examine various processor features, study behaviour of three different processors, and identify the most cost-efficient parameters for a side-core, both in terms of the financial cost and the number transistors. From our experimental analysis, we conclude that a narrow, fast (high clock) in-order pipeline, with small first/second level caches without hardware data prefetch, and a simple branch prediction unit are the desired features in a dedicated side-core for I/O processing. We estimate that this small side-core should consist of one fourth the transistor budget and perform I/O processing with only a 10% performance loss at the same frequency, compared to a big side-core