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Browsing by Author Cao, Ting

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DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time

Author(s)Shi, W.; Wang, Z.; Ren, H., et al
TypeConference paper
Date Published2010
Date CreatedOctober 3-6 2010

iCHAT: Inter-cache hardware-assistant data transfer for heterogeneous chip multiprocessors

Author(s)Gu, Junli; Beckmann, Bradford M; Cao, Ting, et al
TypeConference paper
Date Published2014
Date CreatedAugust 6-8 2014

Looking back and looking forward: Power, performance, and upheaval

Author(s)Esmaeilzadeh, Hadi; Cao, Ting; Yang, Xi, et al
TypeJournal article
Date Published2012
Date Created-

Looking back on the language and hardware revolutions: measured power, performance, and scaling

Author(s)Esmaeilzadeh, Hadi; Cao, Ting; Yang, Xi, et al
TypeConference paper
Date Published2011
Date CreatedMarch 5-11 2011

Portable performance on asymmetric multicore processors

Author(s)Jibaja, Ivan; Cao, Ting; Blackburn, Stephen, et al
TypeConference paper
Date Published2016
Date Created-

The Yin and Yang of power and performance for asymmetric hardware and managed software

Author(s)Cao, Ting; Blackburn, Stephen; Gao, Tiejun, et al
TypeConference paper
Date Published2012
Date CreatedJune 9-13 2012

TL-plane-based multi-core energy-efficient real-time scheduling algorithm for sporadic tasks

Author(s)Zhang, Dongsong; Guo, Deke; Chen, Fangyuan, et al
TypeJournal article
Date Published2012
Date Created-

Virtual Machine Services:An Opportunity for Hardware Customization

Author(s)Cao, Ting; Blackburn, Stephen; McKinley, Kathryn
TypeConference paper
Date Published2011
Date CreatedDecember 4 2011
01_Wang_WADE:_Writeback-Aware_Dynamic_2013.pdf.jpg

WADE: Writeback-Aware Dynamic CachE management for NVM-based main memory system

Author(s)Wang, Zhe; Shan, Shuchang; Cao, Ting, et al
TypeJournal article
Date Published2013
Date Created-

What is happening to power, performance, and software?

Author(s)Esmaeilzadeh, Hadi; Cao, Ting; Yang, Xi, et al
TypeJournal article
Date Published2012
Date Created-
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